1. Field of the Invention
This invention relates generally to a bus control system suitable for use in a data processing system such as an image processing system, and more particularly to such a bus control system in which a data bus connecting a central processing unit to a plurality of peripheral devices can be efficiently used.
2. Prior Art
It has become common that a data processing system, such as an image processing system, includes a central processing unit (CPU) and a plurality of peripheral devices connected to the CPU through a common data bus. Data processing systems of such a construction are also widely used for other various purposes.
In such data processing systems, an exchange of data between a CPU and a device is performed in such a manner that the CPU first designates the device, with which it exchanges data, by outputting address data or the like, and then transmits to or receives from the designated device data using all bit-lines of the common data bus.
With such arrangement, however, when the CPU transmits to or receives from the designated device data each composed of one bit or several bits at most, that is to say, when the CPU transmits or receives data using only a few bit-lines of the common data bus, the remaining bit-lines of the common data bus become idle, so that the common bus can not efficiently be used. Thus, when the CPU transmits to or receives from a number of devices data each composed of a few bits, the number of transmissions or receptions of data the CPU must effect becomes large in spite of the actual amount of data being small. As a result, the dead time in the transmission and reception of data significantly increases.